There are various known technologies which detect failure in transmission paths for signal transmission in a transmission apparatus built using a semiconductor device such as a field-programmable logic array (Field-Programmable Gate Array, FPGA). For example, among such technologies is a failure diagnosis method known as diagnosing a failure location based on a result of comparison between output signals respectively from a pair of bidirectional buffers after test data are inputted into the buffers.
Another example of such technologies is a communication system known as using a serial bus called an inter-integrated circuit (I2C).
FIG. 1 is a diagram illustrating a communication system which uses an I2C.
A communication system 900 includes a master device 901 as a control device, a slave device 102 as a peripheral device, a serial clock (SCL) bus 103, a serial data (SDA) bus 104, and an SCL pull-up resistor 105, and an SDA pull-up resistor 106. The SCL bus 103 is a transmission path for transmitting SCL as a clock signal between the master device 901 and the slave device 102. The SDA bus 104 is a transmission path for transmitting SDA as a data signal between the master device 901 and the slave device 102.
The SCL pull-up resistor 105 is connected to the SCL bus 103, and raises the signal level of the SCL bus 103 to the power supply level when both the master device 901 and the slave device 102 output Hi-Z on the SCL bus 103. The SDA pull-up resistor 106 is connected to the SDA bus 104, and raises the signal level of the SDA bus 104 to the power supply level when both the master device 901 and the slave device 102 output Hi-Z to the SDA bus 104.
The master device 901 includes an I2C master circuit 910, an SCL open-drain signal generation circuit 111, an SCL input buffer 112, an SDA open-drain signal generation circuit 113, and an SDA input buffer 114. The I2C master circuit 910 is a logic circuit for performing predetermined processes. The I2C master circuit 910 outputs an SCL output signal and an SDA output signal as logic output signals, and receives an SCL input signal and an SDA input signal as logic input signals.
The SCL open-drain signal generation circuit 111 has an input terminal connected to the I2C master circuit 910 and an output terminal connected to the SCL pull-up resistor 105 via the SCL bus 103. When the I2C master circuit 910 inputs an SCL output signal representing “0” to the input terminal of the SCL open-drain signal generation circuit 111, the SCL open-drain signal generation circuit 111 outputs SCL representing “0”. When the I2C master circuit 910 inputs an SCL output signal representing “1” to the input terminal of the SCL open-drain signal generation circuit 111, the SCL open-drain signal generation circuit 111 outputs Hi-Z. The SCL open-drain signal generation circuit 111 includes, for example, a tri-state element whose data input terminal is grounded, and to whose control terminal SCL is inputted.
The SCL input buffer 112 buffers SCL inputted to the SCL input buffer 112 via the SCL bus 103, and inputs the buffered SCL signal, serving as an SCL input signal, into the I2C master circuit 910. In outputting Hi-Z, the SCL input buffer 112 buffers an application signal which is applied to the output terminal of the SCL input buffer 112, and inputs the buffered application signal, serving as the as an SCL input signal, into the I2C master circuit 910. For example, the SCL input buffer 112 outputs the SCL input signal depending on the application signal which is applied to the output terminal of the SCL open-drain signal generation circuit 111.
In response to a rise transition of the application signal applied to the output terminal of the SCL open-drain signal generation circuit 111, when the signal level of the application signal becomes higher than a predetermined rise threshold VIH, the SCL input buffer 112 outputs “1”. In a fall transition of the application signal applied to the output terminal of the SCL open-drain signal generation circuit 111, when the signal level of the application signal becomes lower than a predetermined fall threshold VIL, the SCL input buffer 112 outputs “0”.
The configurations and functions of the SDA open-drain signal generation circuit 113 and the SDA input buffer 114 are the same as those of the SCL open-drain signal generation circuit 111 and the SCL input buffer 112, except for inputting and outputting SDA instead of SCL. For this reason, detailed descriptions for the configurations and functions of the SDA open-drain signal generation circuit 113 and the SDA input buffer 114 are omitted herein.
The slave device 102 includes an I2C slave circuit 120, an SCL open-drain signal generation circuit 121, an SCL input buffer 122, an SDA open-drain signal generation circuit 123, and an SDA input buffer 124. Examples of the slave device 102 include an optical module, a delay adjustment device, a temperature monitor device, a clock device, and a power supply device, as communication devices.
The I2C slave circuit 120 is a logic circuit which performs predetermined processes such as detecting various physical quantities. The I2C slave circuit 120 outputs an SCL output signal and an SDA output signal as logic output signals, and receives an SCL input signal and an SDA input signal as logic input signals. The slave device 102 is the logic circuit which performs predetermined processes depending on instructions from the master device 901, and outputs logic output signals, that is to say, SCL as the clock signal and SDA as the data signal, like the master device 901.
The configurations and functions of the SCL open-drain signal generation circuit 121 to the SDA input buffer 124 are the same as those of the SCL open-drain signal generation circuit 111 to the SDA input buffer 114. For this reason, detailed descriptions for the configurations and functions are omitted herein.
I2C defines control signals such as an ACK or NACK bit and clock stretching. When the master device 901 transmits an address signal, a data signal and the like to the slave device 102 via the SDA bus, the slave device 102 indicates its busy state. When the slave device 102 transmits a data signal to the master device 901 via the SDA bus, the master device 901 indicates its busy state.
While the master device 901 and the slave device 102 are being manufactured, and while the communication system 900 is in operation, wiring failure may occur in wiring, or signal transmission paths, in the master device 901 and the slave device 102. The wiring failure includes: a disconnection failure, sometimes referred to as a wiring open failure; and a wiring short-circuit failure. The disconnection failure is a failure in which either the SCL bus 103 or the SDA bus 104 breaks somewhere, and the electrical connection between the master device 901 and the slave device 102 is cut off.
The wiring short-circuit failure is a failure in which the voltage level of either the SCL bus 103 or the SDA bus 104 is fixed to a certain value. The wiring short-circuit failure includes a wiring low short-circuit failure in which the voltage is fixed to the ground level, and a wiring high short-circuit failure in which the voltage level is fixed to the power supply level. The wiring low short-circuit failure occurs, for example, when a failure in either the SCL open-drain signal generation circuit 111 or the SDA open-drain signal generation circuit 113 fixes the voltage level of either the SCL bus 103 or the SDA bus 104 to the ground level. The wiring low short-circuit failure also occurs, for example, when either the SCL bus 103 or the SDA bus 104 is connected to the ground line via conductive matter such as solder scraps, and the voltage level of either the SCL bus 103 or the SDA bus 104 is fixed to the ground level.
The wiring high short-circuit failure occurs, for example, when a failure in either the SCL open-drain signal generation circuit 111 or the SDA open-drain signal generation circuit 113 fixes the voltage level of either the SCL bus 103 or the SDA bus 104 to the power supply level. The wiring high short-circuit failure also occurs, for example, when either the SCL bus 103 or the SDA bus 104 is connected to the power supply line via conductive matter such solder scraps, and the voltage level of either the SCL bus 103 or the SDA bus 104 fixed to the power supply level.
In an electronic system, such as a digital communication system, in which the transmission apparatus is installed, communications between the master device 901 and the slave device 102 are cut off when the I2C fails. Once the communications between the master device 901 and the slave device 102 are cut off, the host controller, such as a Central Processing Unit (CPU), of the master device 901 becomes unable to control the slave device 102, and the operation of the electronic system goes into trouble. For the purpose of quickly detecting the failure in the communications between the master device 901 and the slave device 102, it is desirable that the communication system 900 monitor whether a wiring failure occurs in the I2C, and output a warning signal when detecting a wiring failure.
For example, the master device 901 monitors how long the slave device 102 is in a busy state, based on an NACK state indicated by an ACK or NACK bit in the signal inputted into the master device 901 from the slave device 102 and clock stretching. When the length of time for which the slave device is in the busy state exceeds a certain time, the master device 901 outputs a warning signal indicating the abnormal interface state to the host controller.
The abnormal interface state detected based on the NACK state and the clock stretching, however, means the state where the slave device 102 is not responding. It is not easy for the master device 901 to determine whether the abnormal interface state is a busy state which occurs while the slave device 102 is in normal operation, a failure in the slave device 102, or a wiring failure.
The following is a reference document.    [Document 1] Japanese Laid-open Patent Publication No. 9-34749.